1. Field of the Disclosure
The present disclosure generally relates to electronic devices and, more particularly, to a system and method to substantially reduce active power down standby current in semiconductor memory chips.
2. Brief Description of Related Art
Memory devices are electronic devices that are widely used in many electronic products and computers to store data. A memory device is a semiconductor electronic device that includes a number of memory cells, each cell storing one bit of data. The data stored in the memory cells can be read during a read operation. FIG. 1 is a simplified block diagram showing a memory chip or memory device 12. The memory chip 12 may be part of a DIMM (dual in-line memory module) or a PCB (printed circuit board) containing many such memory chips (not shown in FIG. 1). The memory chip 12 may include a plurality of pins or ball contacts 24 located outside of chip 12 for electrically connecting the chip 12 to other system devices. Some of those pins 24 may constitute memory address pins or address bus 17, data (DQ) pins or data bus 18, and control pins or control bus 19. It is evident that each of the reference numerals 17-19 designates more than one pin in the corresponding bus. Further, it is understood that the schematic in FIG. 1 is for illustration only. That is, the pin arrangement or configuration in a typical memory chip may not be in the form shown in FIG. 1.
A processor or memory controller (not shown) may communicate with the chip 12 and perform memory read/write operations. The processor and the memory chip 12 may communicate using address signals on the address lines or address bus 17, data signals on the data lines or data bus 18, and control signals (e.g., a row address strobe (RAS) signal, a column address strobe (CAS) signal, a chip select (CS) signal, etc. (not shown)) on the control lines or control bus 19. The “width” (i.e., number of pins) of address, data and control buses may differ from one memory configuration to another.
Those of ordinary skill in the art will readily recognize that memory chip 12 of FIG. 1 is simplified to illustrate one embodiment of a memory chip and is not intended to be a detailed illustration of all of the features of a typical memory chip. Numerous peripheral devices or circuits may be typically provided along with the memory chip 12 for writing data to and reading data from the memory cells 26. However, these peripheral devices or circuits are not shown in FIG. 1 for the sake of clarity.
The memory chip 12 may include a plurality of memory cells 26 generally arranged in an array of rows and columns. A row decode circuit 28 and a column decode circuit 30 may select the rows and columns, respectively, in the array in response to decoding an address provided on the address bus 17. Data to/from the memory cells 26 are then transferred over the data bus 18 via sense amplifiers and a data output path (not shown). A memory controller (not shown) may provide relevant control signals (not shown) on the control bus 19 to control data communication to and from the memory chip 12 via an I/O (input/output) circuit 32. The I/O circuit 32 may include a number of data output buffers or output drivers to receive the data bits from the memory cells 26 and provide those data bits or data signals to the corresponding data lines in the data bus 18. The I/0 circuit 32 may also include various memory input buffers and control circuits that interact with the row and column decoders 28, 30, respectively, to select the memory cells for data read/write operations.
The memory controller (not shown) may determine the modes of operation of memory chip 12. Some examples of the input signals or control signals (not shown in FIG. 1) on the control bus 19 include an External Clock (CLK) signal, a Chip Select (CS) signal, a Row Address Strobe (RAS) signal, a Column Address Strobe (CAS) signal, a Write Enable (WE) signal, etc. The memory chip 12 communicates to other devices connected thereto via the pins 24 on the chip 12. These pins, as mentioned before, may be connected to appropriate address, data and control lines to carry out data transfer (i.e., data transmission and reception) operations.
FIG. 2 is a simplified architecture for a portion of the memory device 12 shown in FIG. 1. It is evident that complex circuit details and constituent architectural blocks in the memory chip 12 are omitted from FIG. 2 for the sake of clarity and ease of illustration. As shown in FIG. 2, a data storage or memory array may consist of a matrix of storage bits or memory cells 26 divided into a left memory array 34 and a right memory array 36. Each memory bit being exclusively addressed by a corresponding row and column address (that may be present on the address bus 17). Each row of memory cells may be accessed by a “wordline” (WL), whereas each column of memory cells may be accessed by a “digitline” (DL). Each memory bit or memory cell 26 may be connected to only one corresponding digitline and only one corresponding wordline. In FIG. 2, for ease of illustration, each memory array is shown with one wordline—the wordline 38 in the left array 34 and the wordline 40 in the right array 36. Similarly, each memory array is shown with two digitlines—the digitlines 42 and 44 in the left array 34 and the digitlines 46 and 48 in the right array 36. It is noted that the digitlines 44 and 48 are denoted as “DL*” to indicate the paired nature of the digitlines 42 and 44, and 46 and 48, as is known in the art.
In FIG. 2, two equilibration (EQ) circuits 50 and 52 are shown—each one connected to a corresponding pair of digitlines. Thus, the EQ circuit 50 performs equilibration of digitlines 42 and 44 to the DVC2 voltage level (=Vcc/2 V) before a memory cell access or data sensing operation begins as is known in the art. Similarly, the EQ circuit 52 equlibrates the paired digitlines 46 and 48 to the DVC2 voltage level. A sense amplifier circuit including a pair of cross-coupled PMOS (p-channel metal oxide semiconductor) transistors 54 (P1), 56 (P2), and a pair of cross-coupled NMOS (n-channel MOS) transistors 58 (NI), 60 (N2), connected as depicted in FIG. 2, is shown placed between the four digitlines 42, 44, 46, and 48 and operating on them to perform the data sensing operation as is known in the art. The PMOS transistor pair PI-P2 may be called “Psense-amplifiers” and the NMOS transistor pair N1-N2 may be referred to as “Nsense-amplifiers.”
The Psense- and Nsense-amplifiers 54, 56, 58, 60 work together to detect the data signal voltage in a memory cell and drive the associated digitlines accordingly to Vcc and ground (GNB). For example, in case of the digitlines 42 and 44, the Nsense-amplifiers 58, 60 may drive the low potential digitline (e.g., the digitline 44) to ground and the Psense-amplifiers 54, 56 may drive the high-potential digitline (e.g., the digitline 42) to Vcc. The operation of the sense amplifier circuit (consisting of transistor pairs P1-P2 and N1-N2) may be controlled by a pair of sense amplifier control lines—the ACT (activation) line or signal 61 and the RNLI′ (Row Nsense Latch) line or signal 62 connected as shown in FIG. 2. The ACT line 61 may be active “high” whereas the RNI* signal may be active “low.” Thus, for example, the Psense-amplifiers may be activated when the ACT signal is at a Vcca level (Vcc voltage for the array) or “high”, whereas the Nsense-amplifiers are turned on when the RNL* signal goes to logic zero or ground level.
Isolation (ISO) devices are also important during data storage and sensing operations. These devices are generally NMOS transistors placed between the array digitlines and the sense amplifiers. In FIG. 2, the isolation transistors 64-65 are placed and can control the connection between the digitlines 42 and 44 in the left memory array 34 and the P-N sense amplifier circuitry (consisting of transistor pairs P1-P2 and N1-N2 as noted above), whereas the isolation transistors 67-68 are placed to control the connection between the digitlines 46 and 48 in the right memory array 36 and the P-N sense amplifier circuitry (or P1-P2 and N1-N2 transistor pairs). In other words, if digitline nodes X1 and X2 (not shown) were added in the sense amplifier circuitry in FIG. 2 to correspond with the digitline pair DL-DL*, respectively, the isolation transistor 64 is placed between digitline 42 in the left array and the node X1 and the isolation transistor 67 is placed between the node X1 and the digitline 46 in the right array. Similarly, the isolation transistor 65 is placed between the digitline 44 and the node X2 and the isolation transistor 68 is placed between the node X2 and the 48.
The isolation transistors may function to electrically isolate the two memory arrays 34, 36 so that whenever a wordline fires in one of the arrays, the digitline capacitance in that array is reduced because of the isolation of the other array. Further, the isolation transistors may provide resistance between the adjacent P or Nsense amplifier and the associated digitlines. This resistance may stabilize the sense amplifiers and speed up the data sensing operation by isolating the highly capacitive digitlines. In FIG. 2, the activation/deactivation of isolation transistors is shown controlled by the application of the ISOL signal 66 and the ISOR signal 69 to the corresponding gates of the isolation transistors. The ISOL signal 66 controls the isolation transistors 64-65 for the left array 34, whereas the ISOR signal 69 controls the isolation transistors 67-68 for the right array 36.
FIG. 2 also illustrates the voltage levels of various signals or circuit lines during a memory standby state (e.g., after a row precharge operation is over, but before the row is fired or activated to commence a data access operation thereon). Both the isolation signals—the ISOL signal 66 and ISOR signal 69—may be held at the Vccp level during a row precharge or standby state. As is known in the art, the Vccp voltage level is more than the memory chip's operating voltage level or the “Vcc” level by at least Vth (threshold voltage) of a MOS transistor (NMOS or PMOS). It is known in the art that modern memory circuit designs employ a negative wordline voltage (VNWL) (not shown) to reduce the memory cell leakage current when the corresponding wordline is “off” or “inactive” and to also improve the memory cell refresh characteristics. In FIG. 2, a prior art scheme of maintaining digitlines and wordlines in a memory array in a standby state (e.g., a memory row precharged state) is illustrated via the exemplary voltages illustrated on certain lines. As shown in FIG. 2, during a standby state (i.e., when a row is not fired to commence a data access operation thereon and when sense amplifiers are inactive), the ACT signal line 61 is held at a ground potential (here, at OV), and the RNL* signal 62 is maintained at the Vcc/2 or DVC2 voltage level. During the standby state, the wordlines (e.g., the wordline 38) are precharged to the VNWL level, which, in case of the embodiment in FIG. 2, is negative 0.3 V (−0.3V). However, the digitlines (e.g., the DL 42 and DL* 44) are precharged to the Vcc/2 (or DVC2) voltage level during the standby state. A wordline may be fired when a Vccp voltage level is applied at the wordline (WL signal). Voltage levels for other signals and lines in FIG. 2 during a memory active state (e.g., when a wordline is fired) are not relevant here, and, hence, are not discussed for the sake of brevity.
FIG. 3 shows a prior art circuit scheme to establish desired voltage levels on the sense amplifier control lines (the ACT line 61 for the pair of Psense-amplifiers 54, 56, and the RNL* line 62 for the pair of Nsense-amplifiers 58, 60) of FIG. 2 during memory active and power-down states/modes. It is noted here that during a memory active state (e.g., when a data access operation can be performed), the sense amplifiers PI-P2, N1-N2 are also active; but during a memory stand-by state, the sense amplifiers PI-P2, N I-N2 are not active. While the memory 12 is in its active state, the memory chip 12 may be placed in the memory power-down mode to conserve power, for example, when a memory bank activation is for a long period of time. Thus, in the memory's active power-down mode, the sense amplifiers PI-P2, N1-N2 may remain activated. The memory power-down mode may be contrasted with the memory “sleep” mode where not only the sense amplifiers, but additional circuits in the memory chip 12 may also be placed in an inactive state. It is observed here that a memory controller (not shown) may determine to place the memory chip 12 in a power-down mode (which may be of a longer duration than the routine stand-by mode discussed hereinbefore) to conserve power, especially, for example, when there is a prolonged delay anticipated for a memory access operation, or when the controller is instructed by a microprocessor (not shown) in the system to force the memory chip 12 in the power-down mode.
In FIG. 3, in addition to the P and Nsense amplifier pairs P1-P2 and N1-N2, a pair of driver transistors 70 and 72 are shown connected to corresponding sense amplifier control line “nodes.” For ease of discussion, the ACT line and the ACT line node (where the drain terminal of the PMOS transistor 70 is connected) are referred to by the same reference numeral “61”, and the RNL* line and the RNL* line node (where the drain terminal of the NMOS driver transistor 72 is connected) are also referred to by the same reference numeral “62.” A PSA (Psense amplifier activation) signal 73 may be supplied to the gate terminal of the driver transistor 70, and an NSA (Nsense amplifier activation) signal 74 may be supplied to the gate terminal of the other transistor 72. In FIG. 3, the PSA signal 73 is active “low” and the NSA signal 74 is active “high.” Therefore, a low level on the PSA signal 73 will turn on the PMOS 70, thereby establishing a Vcc (supply voltage) level on the ACT node for line) 61. Similarly, a high level on the NSA signal 74 will turn on the NMOS 72, thereby establishing a ground potential (GND) on the RNL* node (or line) 62. Thus, it is seen from the arrangement in FIG. 3, that the sense amplifier control lines may have opposite potential levels during a memory's active or power-down states. Thus, the voltage on the ACT line 61 may be maintained at a Vcc level during the memory's 12 active and power-down states, but at the ground potential (GND) during the memory standby state as discussed before. On the other hand, the RNL* line 62 may be placed at the ground potential during the memory's active and power-down states, but at the DVC2 (Vcc/2 V) level during the memory standby state as discussed before. The schematic in FIG. 3 is simplified to illustrate only the transistors 70 and 72 connected to the lines 61 and 62, respectively, for applying appropriate voltage levels to the control lines 61-62 during memory active and power-down modes. In practice, as is known in the art, there may be additional driver and logic circuitry associated with each sense amplifier control line 61-62 to apply appropriate voltage levels on the control lines during the memory's stand-by state.
Low power embedded DRAM (Dynamic Random Access Memory) is an increasingly popular solution for mobile personal consumer applications requiring high-speed graphics and long battery life. For example, such memory devices are preferred in mobile phones, PDA's (Personal Digital Assistants), laptop computers, etc., where reduced power requirement or consumption and longer battery life are highly in demand. It is known in the art that the power consumption in a memory device may be reduced by lowering the system supply voltage (Vcc). However, such low supply voltage operation requires reducing the transistor threshold voltages (Vth). Thus, for example, replacing the transistors 54, 56, 58, and 60 by transistors with low or reduced threshold voltages (Vth) will allow low-Vcc sensing operations in the memory chip 12. But, reducing the transistor threshold voltage (Vth) results in increased transistor off current and higher standby power consumption. A low threshold (Vth) transistor in the sense amplifier circuit may produce a relatively big leak current when the sense amplifier is activated (for example, during a memory's active state or power-down state).
It is therefore desirable to devise a memory circuit configuration where low-Vcc sensing scheme may be employed using reduced-Vth sense amplifier transistors, but without increasing the standby current (Idd3) during the memory's active power-down mode. In one prior art method, the power-down standby leakage current (Idd3) from the low-Vth sense amplifiers is reduced by applying a voltage above Vcc level to the PSA line 73 and a voltage below the ground potential to the NSA line 74 during the power down mode. However, such configuration requires periodically exiting the power down mode and performing frequent burst refresh cycles in the memory device to prevent data loss. In another prior art method, the bias voltage for the substrate of the semiconductor memory chip 12 is controlled to reduce the standby leakage current. However, these prior art methods are cumbersome and complicated to implement. These methods may also result in additional memory circuitry to perform various monitoring and control functions, thereby increasing the chip real estate.
Hence, it is desirable to devise a low voltage (Vcc) sensing scheme in a memory device using sense amplifiers with low threshold voltages (Vth) and having reduced standby current (Idd3) during the memory's active power down mode. It is preferred that the sensing scheme be implemented without significant modifications to the sense amplifier layout in a memory chip and without any complex data loss prevention measures.